Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
qsystem_0|rst_controller_001|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
qsystem_0|rst_controller_001|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
qsystem_0|rst_controller_001 33 31 0 31 1 31 31 31 0 0 0 0 0
qsystem_0|rst_controller|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
qsystem_0|rst_controller|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
qsystem_0|rst_controller 33 31 0 31 2 31 31 31 0 0 0 0 0
qsystem_0|mm_interconnect_2|width_adapter_003|check_and_align_address_to_size 46 9 2 9 35 9 9 9 0 0 0 0 0
qsystem_0|mm_interconnect_2|width_adapter_003 165 3 0 3 124 3 3 3 0 0 0 0 0
qsystem_0|mm_interconnect_2|width_adapter_002|check_and_align_address_to_size 46 9 2 9 35 9 9 9 0 0 0 0 0
qsystem_0|mm_interconnect_2|width_adapter_002 165 3 0 3 124 3 3 3 0 0 0 0 0
qsystem_0|mm_interconnect_2|width_adapter_001|uncompressor 58 4 0 4 44 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_2|width_adapter_001 129 4 0 4 160 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_2|width_adapter|uncompressor 58 4 0 4 44 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_2|width_adapter 129 4 0 4 160 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_2|rsp_xbar_mux|arb|adder 8 4 0 4 4 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_2|rsp_xbar_mux|arb 6 0 4 0 2 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_2|rsp_xbar_mux 249 0 0 0 125 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_2|rsp_xbar_demux_001 126 1 2 1 124 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_2|rsp_xbar_demux 126 1 2 1 124 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_2|cmd_xbar_mux_001 126 0 2 0 124 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_2|cmd_xbar_mux 126 0 2 0 124 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_2|cmd_xbar_demux 128 4 2 4 247 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_2|limiter 250 1 1 1 249 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_2|id_router_001|the_default_decode 0 2 0 2 2 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_2|id_router_001 160 0 2 0 160 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_2|id_router|the_default_decode 0 2 0 2 2 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_2|id_router 160 0 2 0 160 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_2|addr_router|the_default_decode 0 5 0 5 5 5 5 5 0 0 0 0 0
qsystem_0|mm_interconnect_2|addr_router 124 0 3 0 124 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_2|hps_f2h_axi_slave_agent|read_rsp_fifo 200 41 0 41 157 41 41 41 0 0 0 0 0
qsystem_0|mm_interconnect_2|hps_f2h_axi_slave_agent|write_rsp_fifo 200 41 0 41 157 41 41 41 0 0 0 0 0
qsystem_0|mm_interconnect_2|hps_f2h_axi_slave_agent|read_burst_uncompressor 58 1 0 1 56 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_2|hps_f2h_axi_slave_agent|check_and_align_address_to_size 46 9 2 9 35 9 9 9 0 0 0 0 0
qsystem_0|mm_interconnect_2|hps_f2h_axi_slave_agent 412 24 19 24 528 24 24 24 0 0 0 0 0
qsystem_0|mm_interconnect_2|hps_console_master_translator_avalon_universal_master_0_agent 202 48 87 48 156 48 48 48 0 0 0 0 0
qsystem_0|mm_interconnect_2|hps_console_master_translator 117 14 2 14 109 14 14 14 0 0 0 0 0
qsystem_0|mm_interconnect_2 164 0 1 0 246 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|rsp_xbar_mux_002|arb|adder 8 4 0 4 4 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_1|rsp_xbar_mux_002|arb 6 0 4 0 2 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|rsp_xbar_mux_002 261 0 0 0 131 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|rsp_xbar_mux_001|arb|adder 8 4 0 4 4 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_1|rsp_xbar_mux_001|arb 6 0 4 0 2 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|rsp_xbar_mux_001 261 0 0 0 131 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|rsp_xbar_mux|arb|adder 8 4 0 4 4 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_1|rsp_xbar_mux|arb 6 0 4 0 2 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|rsp_xbar_mux 261 0 0 0 131 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|rsp_xbar_demux_001 134 9 2 9 388 9 9 9 0 0 0 0 0
qsystem_0|mm_interconnect_1|rsp_xbar_demux 134 9 2 9 388 9 9 9 0 0 0 0 0
qsystem_0|mm_interconnect_1|cmd_xbar_mux_001|arb|adder 12 3 0 3 6 3 3 3 0 0 0 0 0
qsystem_0|mm_interconnect_1|cmd_xbar_mux_001|arb 7 0 1 0 3 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|cmd_xbar_mux_001 390 0 0 0 132 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|cmd_xbar_mux|arb|adder 12 3 0 3 6 3 3 3 0 0 0 0 0
qsystem_0|mm_interconnect_1|cmd_xbar_mux|arb 7 0 1 0 3 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|cmd_xbar_mux 390 0 0 0 132 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|cmd_xbar_demux_002 135 4 3 4 259 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_1|cmd_xbar_demux_001 135 4 3 4 259 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_1|cmd_xbar_demux 135 4 3 4 259 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba|the_min|dc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba|the_min|dc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba|the_min|db_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba|the_min|db_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba|the_min|da_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba|the_min|da_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba|the_min|bc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba|the_min|bc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba|the_min|ac_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba|the_min|ac_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba|the_min|ab_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba|the_min|ab_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba|the_min 31 0 2 0 7 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba|the_burstwrap_increment 7 0 0 0 7 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba|align_address_to_size 40 5 0 5 34 5 5 5 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001|altera_merlin_burst_adapter_full.the_ba 132 0 0 0 130 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter_001 132 0 0 0 130 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|dc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|dc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|db_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|db_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|da_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|da_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|bc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|bc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|ac_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|ac_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|ab_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|ab_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min 31 0 2 0 7 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_burstwrap_increment 7 0 0 0 7 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba|align_address_to_size 40 5 0 5 34 5 5 5 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter|altera_merlin_burst_adapter_full.the_ba 132 0 0 0 130 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|burst_adapter 132 0 0 0 130 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|limiter_002 262 0 0 0 262 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|limiter_001 262 0 0 0 262 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|limiter 262 0 0 0 262 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|id_router_001|the_default_decode 0 6 0 6 6 6 6 6 0 0 0 0 0
qsystem_0|mm_interconnect_1|id_router_001 129 0 2 0 130 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|id_router|the_default_decode 0 6 0 6 6 6 6 6 0 0 0 0 0
qsystem_0|mm_interconnect_1|id_router 129 0 2 0 130 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|addr_router_002|the_default_decode 0 4 0 4 4 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_1|addr_router_002 129 0 3 0 130 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|addr_router_001|the_default_decode 0 4 0 4 4 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_1|addr_router_001 129 0 3 0 130 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|addr_router|the_default_decode 0 4 0 4 4 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_1|addr_router 129 0 3 0 130 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_1|button_pio_s1_translator_avalon_universal_slave_0_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
qsystem_0|mm_interconnect_1|button_pio_s1_translator_avalon_universal_slave_0_agent_rsp_fifo 169 39 0 39 128 39 39 39 0 0 0 0 0
qsystem_0|mm_interconnect_1|button_pio_s1_translator_avalon_universal_slave_0_agent|uncompressor 56 1 0 1 54 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_1|button_pio_s1_translator_avalon_universal_slave_0_agent 333 39 40 39 366 39 39 39 0 0 0 0 0
qsystem_0|mm_interconnect_1|led_pio_s1_translator_avalon_universal_slave_0_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
qsystem_0|mm_interconnect_1|led_pio_s1_translator_avalon_universal_slave_0_agent_rsp_fifo 169 39 0 39 128 39 39 39 0 0 0 0 0
qsystem_0|mm_interconnect_1|led_pio_s1_translator_avalon_universal_slave_0_agent|uncompressor 56 1 0 1 54 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_1|led_pio_s1_translator_avalon_universal_slave_0_agent 333 39 40 39 366 39 39 39 0 0 0 0 0
qsystem_0|mm_interconnect_1|fpga_console_master_translator_avalon_universal_master_0_agent 208 53 97 53 161 53 53 53 0 0 0 0 0
qsystem_0|mm_interconnect_1|hps_h2f_lw_axi_master_agent|align_address_to_size 49 11 1 11 34 11 11 11 0 0 0 0 0
qsystem_0|mm_interconnect_1|hps_h2f_lw_axi_master_agent 437 94 207 94 320 94 94 94 0 0 0 0 0
qsystem_0|mm_interconnect_1|button_pio_s1_translator 116 7 33 7 36 7 7 7 0 0 0 0 0
qsystem_0|mm_interconnect_1|led_pio_s1_translator 116 7 33 7 70 7 7 7 0 0 0 0 0
qsystem_0|mm_interconnect_1|fpga_console_master_translator 117 14 2 14 109 14 14 14 0 0 0 0 0
qsystem_0|mm_interconnect_1 294 0 1 0 138 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_0|width_adapter_001|check_and_align_address_to_size 44 9 2 9 33 9 9 9 0 0 0 0 0
qsystem_0|mm_interconnect_0|width_adapter_001 170 3 3 3 129 3 3 3 0 0 0 0 0
qsystem_0|mm_interconnect_0|width_adapter|uncompressor 56 4 0 4 42 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_0|width_adapter 134 3 0 3 165 3 3 3 0 0 0 0 0
qsystem_0|mm_interconnect_0|rsp_xbar_mux_001 167 0 2 0 165 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_0|rsp_xbar_mux 167 0 2 0 165 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_0|rsp_xbar_demux 168 4 2 4 329 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_0|cmd_xbar_mux|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_0|cmd_xbar_mux|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_0|cmd_xbar_mux 331 0 0 0 166 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_0|cmd_xbar_demux_001 167 1 2 1 165 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_0|cmd_xbar_demux 167 1 2 1 165 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|dc_sub|subtract 19 1 0 1 9 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|dc_sub 18 2 0 2 9 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|db_sub|subtract 19 1 0 1 9 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|db_sub 18 2 0 2 9 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|da_sub|subtract 19 1 0 1 9 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|da_sub 18 2 0 2 9 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|bc_sub|subtract 19 1 0 1 9 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|bc_sub 18 2 0 2 9 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|ac_sub|subtract 19 1 0 1 9 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|ac_sub 18 2 0 2 9 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|ab_sub|subtract 19 1 0 1 9 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min|ab_sub 18 2 0 2 9 2 2 2 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_min 35 0 2 0 8 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba|the_burstwrap_increment 8 0 0 0 8 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba|align_address_to_size 38 5 0 5 32 5 5 5 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter|altera_merlin_burst_adapter_full.the_ba 131 0 0 0 129 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_0|burst_adapter 131 0 0 0 129 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_0|id_router|the_default_decode 0 4 0 4 4 4 4 4 0 0 0 0 0
qsystem_0|mm_interconnect_0|id_router 129 0 2 0 129 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_0|addr_router_001|the_default_decode 0 3 0 3 3 3 3 3 0 0 0 0 0
qsystem_0|mm_interconnect_0|addr_router_001 165 3 3 3 165 3 3 3 0 0 0 0 0
qsystem_0|mm_interconnect_0|addr_router|the_default_decode 0 3 0 3 3 3 3 3 0 0 0 0 0
qsystem_0|mm_interconnect_0|addr_router 165 3 3 3 165 3 3 3 0 0 0 0 0
qsystem_0|mm_interconnect_0|trace_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
qsystem_0|mm_interconnect_0|trace_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo 169 39 0 39 128 39 39 39 0 0 0 0 0
qsystem_0|mm_interconnect_0|trace_memory_s1_translator_avalon_universal_slave_0_agent|uncompressor 56 1 0 1 54 1 1 1 0 0 0 0 0
qsystem_0|mm_interconnect_0|trace_memory_s1_translator_avalon_universal_slave_0_agent 332 39 39 39 364 39 39 39 0 0 0 0 0
qsystem_0|mm_interconnect_0|hps_h2f_axi_master_agent|align_address_to_size 48 0 1 0 33 0 0 0 0 0 0 0 0
qsystem_0|mm_interconnect_0|hps_h2f_axi_master_agent 561 120 245 120 424 120 120 120 0 0 0 0 0
qsystem_0|mm_interconnect_0|trace_memory_s1_translator 114 8 16 8 87 8 8 8 0 0 0 0 0
qsystem_0|mm_interconnect_0 245 0 0 0 151 0 0 0 0 0 0 0 0
qsystem_0|button_pio 7 0 0 0 32 0 0 0 0 0 0 0 0
qsystem_0|led_pio 38 28 28 28 36 28 28 28 0 0 0 0 0
qsystem_0|fpga_console|rst_controller|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
qsystem_0|fpga_console|rst_controller|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
qsystem_0|fpga_console|rst_controller 33 31 0 31 1 31 31 31 0 0 0 0 0
qsystem_0|fpga_console|p2b_adapter 14 8 2 8 20 8 8 8 0 0 0 0 0
qsystem_0|fpga_console|b2p_adapter 22 0 2 0 12 0 0 0 0 0 0 0 0
qsystem_0|fpga_console|transacto|p2m 48 0 0 0 82 0 0 0 0 0 0 0 0
qsystem_0|fpga_console|transacto 48 0 0 0 82 0 0 0 0 0 0 0 0
qsystem_0|fpga_console|p2b 22 0 0 0 10 0 0 0 0 0 0 0 0
qsystem_0|fpga_console|b2p 12 0 0 0 20 0 0 0 0 0 0 0 0
qsystem_0|fpga_console|fifo 53 41 0 41 10 41 41 41 0 0 0 0 0
qsystem_0|fpga_console|timing_adt 12 0 3 0 9 0 0 0 0 0 0 0 0
qsystem_0|fpga_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser|crosser 4 1 0 1 1 1 1 1 0 0 0 0 0
qsystem_0|fpga_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser 13 0 0 0 9 0 0 0 0 0 0 0 0
qsystem_0|fpga_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|output_stage 12 0 0 0 10 0 0 0 0 0 0 0 0
qsystem_0|fpga_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser 14 0 0 0 10 0 0 0 0 0 0 0 0
qsystem_0|fpga_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_inserter 12 0 0 0 9 0 0 0 0 0 0 0 0
qsystem_0|fpga_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_remover 12 1 0 1 9 1 1 1 0 0 0 0 0
qsystem_0|fpga_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|node 4 0 0 0 8 0 0 0 0 0 0 0 0
qsystem_0|fpga_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming 12 1 0 1 16 1 1 1 0 0 0 0 0
qsystem_0|fpga_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming 11 0 0 0 15 0 0 0 0 0 0 0 0
qsystem_0|fpga_console|jtag_phy_embedded_in_jtag_master 11 0 0 0 11 0 0 0 0 0 0 0 0
qsystem_0|fpga_console 36 0 0 0 70 0 0 0 0 0 0 0 0
qsystem_0|hps_console|rst_controller|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
qsystem_0|hps_console|rst_controller|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps_console|rst_controller 33 31 0 31 1 31 31 31 0 0 0 0 0
qsystem_0|hps_console|p2b_adapter 14 8 2 8 20 8 8 8 0 0 0 0 0
qsystem_0|hps_console|b2p_adapter 22 0 2 0 12 0 0 0 0 0 0 0 0
qsystem_0|hps_console|transacto|p2m 48 0 0 0 82 0 0 0 0 0 0 0 0
qsystem_0|hps_console|transacto 48 0 0 0 82 0 0 0 0 0 0 0 0
qsystem_0|hps_console|p2b 22 0 0 0 10 0 0 0 0 0 0 0 0
qsystem_0|hps_console|b2p 12 0 0 0 20 0 0 0 0 0 0 0 0
qsystem_0|hps_console|fifo 53 41 0 41 10 41 41 41 0 0 0 0 0
qsystem_0|hps_console|timing_adt 12 0 3 0 9 0 0 0 0 0 0 0 0
qsystem_0|hps_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser|crosser 4 1 0 1 1 1 1 1 0 0 0 0 0
qsystem_0|hps_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser 13 0 0 0 9 0 0 0 0 0 0 0 0
qsystem_0|hps_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|output_stage 12 0 0 0 10 0 0 0 0 0 0 0 0
qsystem_0|hps_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser 14 0 0 0 10 0 0 0 0 0 0 0 0
qsystem_0|hps_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_inserter 12 0 0 0 9 0 0 0 0 0 0 0 0
qsystem_0|hps_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_remover 12 1 0 1 9 1 1 1 0 0 0 0 0
qsystem_0|hps_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|node 4 0 0 0 8 0 0 0 0 0 0 0 0
qsystem_0|hps_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming 12 1 0 1 16 1 1 1 0 0 0 0 0
qsystem_0|hps_console|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming 11 0 0 0 15 0 0 0 0 0 0 0 0
qsystem_0|hps_console|jtag_phy_embedded_in_jtag_master 11 0 0 0 11 0 0 0 0 0 0 0 0
qsystem_0|hps_console 36 0 0 0 70 0 0 0 0 0 0 0 0
qsystem_0|trace_memory|the_altsyncram|auto_generated|mux2 65 0 0 0 32 0 0 0 0 0 0 0 0
qsystem_0|trace_memory|the_altsyncram|auto_generated|decode3 2 0 0 0 2 0 0 0 0 0 0 0 0
qsystem_0|trace_memory|the_altsyncram|auto_generated 53 0 0 0 32 0 0 0 0 0 0 0 0
qsystem_0|trace_memory 56 0 1 0 32 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|dll 2 0 0 0 7 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|oct 1 0 0 0 32 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|c0 228 173 8 173 280 173 173 173 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|seq 0 0 0 0 0 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst 135 0 3 0 36 0 0 0 10 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst 135 0 3 0 36 0 0 0 10 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst 135 0 3 0 36 0 0 0 10 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst 135 0 3 0 36 0 0 0 10 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].uclk_generator 1 0 0 0 2 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated 3 0 0 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ureset_n_pad 7 1 0 1 1 1 1 1 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ucmd_pad 37 1 0 1 6 1 1 1 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ubank_pad 19 1 0 1 3 1 1 1 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|uaddress_pad 91 1 0 1 15 1 1 1 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[24].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[23].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[22].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[21].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[20].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[19].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[18].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[17].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[16].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[15].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[14].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[13].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[12].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[11].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[10].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[9].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[8].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[7].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[6].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[5].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[4].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[3].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[2].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[1].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[0].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads 118 0 5 0 27 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads 633 58 118 58 220 58 58 58 40 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy|memphy_ldc 10 0 1 0 4 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0|umemphy 975 1 2 1 366 1 1 1 40 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|p0 878 545 0 545 130 545 545 545 40 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst|pll 2 1 2 1 12 1 1 1 0 0 0 0 0
qsystem_0|hps|hps_io|border|hps_sdram_inst 1 0 0 0 31 0 0 0 40 0 0 0 0
qsystem_0|hps|hps_io|border 0 0 0 0 0 0 0 0 0 0 0 0 0
qsystem_0|hps|hps_io 8 0 0 0 49 0 0 0 50 0 0 0 0
qsystem_0|hps|fpga_interfaces 379 0 0 0 457 0 0 0 0 0 0 0 0
qsystem_0|hps 387 0 0 0 506 0 0 0 50 0 0 0 0
qsystem_0 12 0 0 0 53 0 0 0 50 0 0 0 0